-- 直流电机控制电路
-- 通过方波信号的直流电压与占空比的关系，即占空比越大，电压越大


entity pwm is
    port(
        clk : in std_logic;
        clear : in std_logic;        
        duty : in std_logic_vector(3 downto 0); -- period中空数据的数量（duty_cycle是占空比的意思，这个不是）
        period : in std_logic_vector(3 downto 0);   -- 周期(时钟周期数)
        pwm : out std_logic     -- 脉冲宽度调制（1， 0）
    );
end entity;

architecture behave of pwm is
    signal cnt : std_logic_vector(3 downto 0);
begin

    -- cnt
    process(clk, clear) begin
        if clear = '1' then
            cnt <= "0000";
        elsif rising_edge(clk) then
            if cnt = period - 1 then
                count <= "0000";
            else
                count <= count + 1;
            end if;
        end if;
    end process;

    process(clk) begin
        if rising_edge(clk) then
            if count <= duty then 
                pwm <= '0';
            else
                pwc <= '1';
            end if;
        end if;
    end process;

end behave;
